Cross-couple contact (XC) is mandatory in static random-access memory (SRAM) bit cells to connect an internal node (Q/QB) of an inverter to the gate of another inverter. XC is conventionally achieved by connecting a source/drain contact (TS) to a gate contact (CB), and is generally area efficient for fin field effect transistors (FinFETs) and planar FETs. However, VFET architecture is different than FinFETs or planar FETs, and the conventional XC or similar approaches are neither suitable nor area efficient for VFETs.
On the other hand, the architecture of VFETs offer a unique design opportunity: (i) the SRAM internal node (Q/QB) is naturally achieved through the design of the shared bottom active region (RX), and (ii) pass gate (PG) 1/PG 2 source/drain (S/D) are naturally connected to Q/QB. A buried contact (BC) XC can advantageously help SRAM area scaling. However, conventional BC integration is not self-aligned, therefore limiting bit cell scaling benefits. Furthermore, there is a risk of shorts between a buried contact and a self-aligned (SA) gate (PC). As a result, to limit the risk of shorts and ensure proper contact, design rules limit bit cell scaling.
A need, therefore, exists for devices with self-aligned BC relaxing or voiding critical design rules, and enabling significant additional scaling, process robustness, and control relief.